Nonvolatile semiconductor memory devices represented by NAND flash memories are manufactured by using semiconductor wafer processes. The increase in capacity and reduction in power consumption and cost of the nonvolatile semiconductor memory devices have been realized with the progress of two-dimensional miniaturization techniques at wafer processes. On the other hand, storage devices that include a three-dimensional memory array having a plurality of memory layers laid on each other are being developed as next-generation nonvolatile memory devices. To increase the capacity of a three-dimensional memory cell array, it is necessary to miniaturize a plurality of word lines controlling memory cells and increase the number of stacks of the memory cell array. However, the miniaturization of word lines and high-level stacking could collapse the stacking structure of the memory cell array in some cases.